1. Field of the Invention
The present invention is related to an electro-chemical machining apparatus, more specifically to an electro-chemical machining apparatus for smoothing a rough surface on a metal film forming process.
2. Related Art
High scale integration and miniaturization of semiconductor devices have accelerated the introduction of narrower, fine pitch and multilayered wirings, thus increasing the significance of multilayer wiring techniques in semiconductor fabrication processes.
Although it has been conventional to use aluminum as wiring material in multilayer semiconductor devices, many attempts have been made to develop new wiring processes replacing aluminum with copper as the wiring material so as to reduce signal propagation delay in recent 0.25 μm or less design rules. The use of copper is advantageous in that it permits achieving both low electric resistance and high endurance to electro migration.
As far as copper wiring process is concerned, it is typical to use the so-called damascene process in which metal is buried in a groove wiring pattern, e.g., formed in advance in an interlayer insulation film. Then, a chemical mechanical polishing (CMP) process is applied to form the wiring by removing excessive metal film. The damascene process is advantageous in that no etching of the wiring is required and the interlayer insulation film to be formed thereon is essentially flat, thereby simplifying the process. Also, significant reduction in wiring process is achieved by the dual damascene process in which not only the wiring grooves but also contact holes are formed in the interlayer insulation film for simultaneously burying metal in the wiring grooves and the contact holes.
In addition, one example of copper wiring process according to the above-mentioned dual damascene process will be described with reference to the accompanying drawings.
Firstly, as illustrated in FIG. 34, an interlayer insulating film 302 made of silicon oxide, for example, is formed by, e.g., low pressure chemical vapor deposition (CVD) on a semiconductor substrate 301 made of, for example, silicon having impurity diffused regions (not shown in the drawing) selectively formed thereon.
Next, as illustrated in FIG. 35, contact holes (CH) leading to the impurity diffused regions of the semiconductor substrate 301 and grooves (M) of a designated wiring pattern making electrical connection to the impurity diffused regions are formed using conventional photolithography and etching techniques.
FIG. 36 illustrates a next step in which a barrier film 305 is provided on the interlayer insulating film 302 as well as in the contact holes (CH) and the wiring grooves (M). The barrier film 305 is made from such materials, e.g., Ta, Ti, TaN, TiN, etc. using a conventional sputtering technique. In the case where copper is used as the wiring material and silicon oxide is used as the interlayer insulation film, the barrier layer 305 is provided to prevent copper oxidation as copper exhibits high diffusion coefficient in relation to silicon oxide.
Next, as illustrated in FIG. 37, copper is deposited onto the barrier film 305 to a designated film thickness through a conventional sputtering technique so as to form a seed film 306.
FIG. 38 illustrates a subsequent step to provide a copper film 307 in such a manner that the contact holes (CH) and the wiring grooves (M) are filled with copper by, e.g., electroplating, CVD, sputtering or other techniques.
FIG. 39 illustrates a subsequent step for removing excessive portions of the copper film 307 and the barrier film 305 on the interlayer insulation film 302 by applying the CMP technique, thereby providing a smooth surface.
The above steps provide copper wirings 308 and contacts 309. Then, the aforementioned steps are repeated on the wirings 308 to provide multilayered wirings.
However, the aforementioned copper wiring using the dual damascene process might cause significant damages to the semiconductor substrate because the conventional CMP method for removing excessive copper film 307 and smoothing the surface has a drawback in which the a polishing tool applies pressure onto the copper film. Especially, in the case where an organic insulation film having low mechanical strength and low dielectric constant as the interlayer insulation film, the abovementioned damages are not negligible because it may result in defects such as cracks in the interlayer insulation film or peeling the interlayer insulation film out of the semiconductor substrate.
Also, because of different removing characteristics between the interlayer insulating film 302, the copper film 307 and the barrier film 305, the wirings 308 tend to present problems such as dishing, erosion (thinning), recess, etc.
As shown in FIG. 40, dishing is a phenomenon causing a dimple by excessive removal at a central portion of the wiring, especially in a relatively wide, e.g., wiring of about 100 μm wide under, e.g., 0.18 μm design rule. The dishing is one of the primary causes of wiring problems due to insufficient cross section area of the wiring 308 leading to increased wiring electric resistance. Such dishing is most likely to occur when relatively soft copper or aluminum is used as the wiring material.
As shown in FIG. 41, erosion is a phenomenon that causes excessive removal of the area where wiring pattern density is high, e.g., 1.0 μm wirings being formed in a range of 3000 μm with density of about 50%. If such erosion occurred, a cross section area of the wiring is reduced in such an amount that might result in problematic wiring electric resistance.
A recess is shown in FIG. 42, in which steps are created at the boundary of the interlayer insulation film 302 and the wirings 308 by lowering the wirings 308. Again, cross section area of the wirings is insufficient in this case and might result in wiring electric resistance defects.
On the other hand, in the surface smoothing and removing steps of the excessive copper film 307 by the CMP process, a polishing rate represented by the amount of removing copper in a predetermined time span is required to be set to, e.g., 500 nm/min or higher in order to efficiently removing the copper film.
In order to increasing the polishing rate, it is necessary to apply higher pressure to the polishing tool onto the wafer. However, increased pressure to the polishing tool may result in scratches (SC) or chemical damages (CD) on the surface of wirings, as shown in FIG. 43. This is most likely to occur in soft copper, thereby causing troubles such as open circuits, short circuits, defective wiring resistance, etc. Also, increased pressure applied onto the polishing tool may result in increased likelihood of the aforementioned scratches, peeling of the interlayer insulation film, dishing, erosion and recess to occur.